The present invention relates in general to apparatus for verifying electronic circuit designs and more specifically to his invention relates to the design and use of electric interconnect test circuitry. In particular, the present invention relates to the circuitry and test methods used to locate damaged, high impedance or high capacitive paths between interconnected programmable chips.
Hardware emulation systems are devices designed for verifying electronic circuit designs prior to fabrication as chips or printed circuit boards. These systems are typically built from programmable logic chips (logic chips) and programmable interconnect chips (interconnect chips). The term xe2x80x9cchipxe2x80x9d as used herein refers to integrated circuits. Examples of logic chips include reprogrammable logic circuits such as field-programmable gate arrays (xe2x80x9cFPGAsxe2x80x9d), which include both off-the-shelf products and custom products. Examples of interconnect chips include reprogrammable FPGAs, multiplexer chips, crosspoint switch chips, and the like. Interconnect chips can be either off-the-shelf products or custom designed.
Prior art emulation systems have generally been designed so that each signal in an electronic circuit design to be emulated is mapped to one or more physical metal lines (xe2x80x9cwiresxe2x80x9d) within a logic chip. Signals which must go between logic chips are mapped to one or more physical pins on a logic chip and one or more physical traces on printed circuit boards which contain the logic and interconnect chips.
The one-to-one mapping of design signals to physical pins and traces in prior art emulation systems leads to the requirement that the emulation system contain at least as many logic chip pins and printed circuit board traces as there are design signals to be routed between logic chips. Such an arrangement requires the use of very complex and expensive integrated circuit packages, printed circuit boards and circuit board connectors to construct the emulation system. The high cost of these components, which in turn increases the cost of the hardware logic emulation system, is a factor in limiting the number of designers who can afford, and therefore, benefit from, the advantages provided by hardware emulation systems.
Furthermore, integrated circuit fabrication technology is allowing the use of ever decreasing feature sizes. Thus, the logic density of logic chips (i.e., the number of logic gates that can be implemented therein) has increased dramatically. The increase in the number of logic gates that can be implemented or emulated in a single logic chip, however, has not been met with an increase in the number of pins (i.e., leads) available for inputs, outputs, clocks and the like on the chip""s package. The number of pins on an integrated circuit package is limited by the available perimeter of the chip. Furthermore, the capability of the wire-bonding assembly equipment used to connect the bonding pads on integrated circuit dice to the pins on the package has increased slowly over time. Thus, there is an increasing mismatch between the amount of logic available on a logic chip and the number of pins available to connect the logic to the outside world. This results in poor average utilization of the logical capacity of the logic chips, which increases the cost of a hardware emulation system necessary for emulation of a given sized electronic circuit design.
Time-multiplexing is a technique that has been used for sharing a single physical wire or pin between multiple logical signals in certain types of systems where the cost of each physical connection is very high. Such systems include telecommunication systems. Time-multiplexing, however, has not been commonly used in hardware emulation systems such as those available from Quickturn Design Systems, Inc., Mentor Graphics. Corporation, Aptix Corporation, and others because the use of prior art time-multiplexing methods significantly reduced the speed at which the emulated circuit could operate. Furthermore, prior art time-multiplexing techniques makes it difficult to preserve the correct asynchronous behavior of an embedded design in the hardware emulation system.
As discussed, one function of hardware emulation systems is to verify the functionality of an integrated circuit. Typically, when a circuit designer or engineer designs an integrated circuit, the design is represented in the form of a xe2x80x9cnetlistxe2x80x9d description of the design. A netlist description (or xe2x80x9cnetlistxe2x80x9d, as it is referred to by those of ordinary skill in the art) is a description of the integrated circuit""s components and electrical interconnections between the components. The components include all those circuit elements necessary for implementing a logic circuit, such as combinational logic (e.g., gates) and sequential logic (e.g., flip-flops and latches). Prior art emulation systems analyzed the user""s circuit netlist prior to implementing the netlist into the hardware emulation system. This analysis included the steps of separating the various circuit paths of the design into clock paths, clock qualifiers and data paths. A method for performing this analysis and separation is disclosed in U.S. Pat. No. 5,475,830 by Chen et al, which is assigned to the same assignee as the present invention. The disclosure of U.S. Pat. No. 5,475,830 is incorporated herein by reference in its entirety. The techniques disclosed in U.S. Pat. No. 5,475,830 have been used in prior art emulation systems such as the System Realizer(trademark) brand hardware emulation system from Quickturn Design Systems, Inc., Mountain View, Calif. However, the techniques disclosed therein have not been used in combination with any type of time-multiplexing.
Other prior art hardware emulation systems such as those available from Virtual Machine Works (now IKOS), ARKOS (now Quickturn Design Systems, Inc. (the assignee of the present application), a Cadence Company) and IBM have attempted to use time-multiplexing of design signals onto a single physical logic chip pin and printed circuit board trace to seek lower hardware cost for a given size of electronic design to be emulated. These prior art emulation systems, however, alter or re-synthesize clock paths in an attempt to maintain correct circuit behavior. This alteration or re-synthesis process works predictably for synchronous designs. However, altering or re-synthesizing the clock paths in an asynchronous design can lead to inaccurate or misleading emulation results. Since most circuit designs have asynchronous clock architectures, the need to alter or re-synthesize the clock paths is a large disadvantage.
In addition, prior art hardware emulation machines using time-multiplexing have suffered from low operating speed. This is a consequence of re-synthesizing the clock paths. In these machines, a number of internal machine cycles are required to emulate one clock cycle of a design. Thus, the effective operating speed for the emulated design is typically many times slower than the maximum clock rate of the emulation system itself. If there are multiple asynchronous clocks in the design to be emulated, the slowdown typically becomes even worse because of the need to evaluate the state of the emulated design between each pair of input clock edges.
Prior art hardware emulation machines using time-multiplexing also require complex software for synchronizing the flow of many design signals over a single physical logic chip pin or printed circuit board trace. Each design signal must be timed so that it has the correct value at the instant it is needed in other parts of the system to compute other design signals. This timing analysis software (also known as scheduling software) adds to the complexity of the emulator and to the time needed to compile a circuit design into the emulator.
Furthermore, prior art hardware emulation machines which use time-multiplexing only use a simple form of time-multiplexing which requires minimal hardware but uses a large amount of power (e.g., current) and requires a complex system design.
In addition, as is seen in the prior art, emulation systems are generally comprised of large numbers of integrated circuits having input/output pins connected together. In emulation systems, including the various embodiments of the present invention, these connections are such that every programmable chip input/output pin is physically connected to other programmable chip input/output pins via one of two topologies. The first topology, which can be called xe2x80x9clocal direct connectxe2x80x9d, is where the chips being interconnected are located on the same printed circuit board (xe2x80x9cPCBxe2x80x9d) and are connected via PCB traces. The second topology, which can be called xe2x80x9cdistant connectxe2x80x9d, is where two chips on different PCBs are connected via separate PCB traces joined by connectors. This specification defines a net as a connection made between different input/output pins via a conductive medium that may have a bi-directional buffer in between.
In emulation systems, most nets are simple point-to-point nets. A point-to-point net is defined as an input/output pin on a first device that is connected to a input/output pin on a second device. Note that there are some situations, however, where there may be more than two pins on a net. As one example, the can be one pin on the first device connected to a pin on second device, a pin on third device, and possibly another pin on a fourth device.
Because of the large number of nets (i.e., pin-to-pin interconnections) emulation systems have, emulation systems such as those manufactured by Quickturn Design Systems, Inc. are very complicated physical structures. The PCBs that are used can have over thirty layers. In addition, the connectors used to interconnect boards can have hundreds of pins. Because of the complicated nature of emulation systems, manufacturing defects can arise that cause nets to be shorted, have high resistance, and/or high capacitance. If any one of the nets has such a manufacturing defect, the performance of the emulation system will be degraded, or the emulation system may not work at all. At the same time, it is very difficult to test each and every net for a defect.
Thus, there is a need for a hardware emulation system which has very high logical capacity, fast compile times, less complex software, simplified mechanical design and reduced power consumption. There is also a need for a method and apparatus for testing the nets of the emulation system.
A new type of hardware emulation system is disclosed and claimed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board traces but which does not have the limitations of low operating speed and poor asynchronous performance. Additional methods to multiplex multiple signals onto a single physical interconnection which are suitable for hardware emulation but do not have the disadvantages of high power and complex system design are also disclosed.
In the preferred embodiment, time-multiplexing is performed on clock qualifier paths (a clock qualifier is any signal which is used to gate a clock signal) and data paths in a design but not on clock paths (a clock path is the path between the clock signal and the clock source from which the clock signal is derived).
The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, each having internal circuitry which can be reprogrammably configured to provide at least combinatorial logic elements and storage elements. The programmable logic devices also have programmable input/output terminals which can be reprogrammably interconnected to selected ones of functional elements of the logic devices. The reprogrammable logic devices have input demultiplexers and output multiplexers implemented at each input/output terminal. The input demultiplexers receive a time-multiplexed signal and divide it into one or more internal signals. The output multiplexers combine one or more internal signals onto a single physical interconnection.
The invention also comprises a plurality of reprogrammable interconnect devices, each of which have input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected input/output terminals. The reprogrammable interconnect devices also have input demultiplexers and output multiplexers implemented at each input/output terminal. The input demultiplexers receive a time-multiplexed input signal and divide it into one or more component signals. The output multiplexers combine one or more component signals onto a second single physical interconnection.
The invention also comprises a set of fixed electrical conductors connecting the programmable input/output terminals on the reprogrammable logic devices to the input/output terminals on the reprogrammable interconnect devices.
In another aspect of the present invention, a logic analyzer is integrated into the logic emulation system which provides complete visibility of the design undergoing emulation. The logic analyzer of the present invention is distributed, in that its components are integrated into many of the resources of the emulation system. The logic analyzer of the present invention comprises having at least scan chains programmed into each of the logic chips of the logic boards. The scan chains are comprised of at least one flip-flop. The scan chains are programmably connectable to selected subsets of sequential logic elements of the design undergoing emulation.
The logic analyzer further comprises at least one memory device which is in communication with the scan chain. This memory device stores data from the sequential logic elements of the logic design undergoing emulation. Control circuitry communicates with the logic chips of the emulation system and generates logic analyzer clock signals which clock the scan chains. The control circuitry also generates trigger signals when predetermined combinations of signals occur in the logic chips.
In another aspect of the present invention, a method for dynamically testing interconnections between a first integrated circuit and a second integrated circuit (e.g., the interconnections between a programmable logic chip and a programmable interconnect chip, or the interconnections between two different programmable interconnect chips) is disclosed. The method involves the steps of programming a first cell into the first chip such that the first cell is in electrical communication with a pin on the first chip. The first cell can comprise a first storage element. A second cell is programmed into the second chip such that the second cell is in electrical communication a pin on the second chip. The second cell can comprise a second storage element. A predetermined data value is programmed into the first cell while a predetermined expected data value is programmed into the second cell. The predetermined data value is transmitted from the first chip, through the interconnect, to the second chip. The predetermined data value received by the second chip is compared to the predetermined expected value. An error flag is output if the predetermined data value received by the second chip and the predetermined expected value do not match.
In one embodiment of this method, the first cell comprises a first and a second shift register wherein outputs from the first and second shift register are input to a multiplexer. A driver receives an output from this multiplexer, which controls whether the output from the multiplexer is placed onto the interconnect.
In an embodiment of this invention, the second cell comprises a third and a fourth shift register wherein outputs from the third and fourth shift register are input to a multiplexer, which controls whether the output from the multiplexer is placed onto the interconnect.
In another embodiment of the present invention, the first cell comprises a plurality of registers for storing the predetermined data values. This plurality of registers is in electrical communication with a multiplexer that selects which predetermined data value is placed onto the interconnect. In this embodiment, the second cell comprises a plurality of registers for storing the predetermined expected values This plurality of registers is in electrical communication with a multiplexer that selects which predetermined expected value is compared to the received predetermined data value.
In another aspect of the present invention, an apparatus for testing integrity of interconnections between a first integrated circuit and a second integrated circuit is disclosed. The first integrated circuit comprises a first pin, while the second integrated circuit comprises a second pin. The first and second pin are in electrical communication with each other through an interconnect. The apparatus of this aspect of the invention comprises a first cell in electrical communication with the first pin on the first integrated circuit. The first cell comprises a first pattern match circuit. The first cell stores a predetermined data value. The apparatus of this aspect of the invention also comprises a second cell in electrical communication with the second pin on the second integrated circuit. The second cell comprises a second pattern match circuit. The second cell stores a predetermined expected value.
In an embodiment of this aspect of the present invention, the first cell comprises a first shift register and a second shift register. The first shift register comprises a first register and a second register while the second shift register comprises a third register and a fourth register. The first cell comprises a first multiplexer and a first driver. The first register is in electrical communication with the first pattern match circuit while the second register is in electrical communication with the first multiplexer. The third register is in electrical communication with the first pattern match circuit while the fourth register is in electrical communication with the first multiplexer. In this embodiment of the invention, the second cell comprises a third shift register and a fourth shift register. The third shift register comprises a fifth register and a sixth register. The fourth shift register comprises a seventh register and an eighth register. The second cell further comprises a second multiplexer and a second driver. The fifth register is in electrical communication with the second pattern match circuit. The sixth register is in electrical communication with the second multiplexer while the seventh register is in electrical communication with the second pattern match circuit. The eighth register is in electrical communication with the second multiplexer.
In another embodiment of this aspect of the invention, the first cell comprises a plurality of first registers. The plurality of first registers output to a first multiplexer while the first multiplexer outputs to the first pattern match circuit and to a first driver. The first driver outputs the predetermined data value to the first pin on the first integrated circuit. This first pin is supposed to be in electrical communication with the second pin on the second integrated circuit though a interconnect structure. This is the interconnect structure being tested for integrity. In this embodiment, the second cell comprises a plurality of second registers. This plurality of second registers outputs to a second multiplexer while the second multiplexer outputs to a second pattern match circuit. The second pattern match circuit compares the predetermined expected value with the predetermined data value.